Content addressable memory array system with multiplexed status and command information
US4888731A · kind A · utility
28Cited by
1References
10Claims
0Family size
Assignee
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Key dates
| Filing date | May 11, 1988 |
| Grant date | Dec 19, 1989 |
| Priority date | — |
| Expiry date | May 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90339
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the commands including a command write command, a data write command, a data read command, and a status read command, the command write and the status read commands being encodable in S bits or less, and multiplexing means for supplying selected ones of the commands to the I/O bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.