Trilayer microlithographic process using a silicon-based resist as the middle layer
US4891303A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 1988 |
| Grant date | Jan 2, 1990 |
| Priority date | — |
| Expiry date | May 26, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0274
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for patterning an integrated circuit workpiece (10) includes forming a first layer (16) of organic material on the workpiece surface to a depth sufficient to allow a substantially planar outer surface (36) thereof. A second, polysilane-based resist layer (22) is spin-deposited on the first layer (16). A third resolution layer (24) is deposited on the second layer (22). The resolution layer (24) is selectively exposed and developed using standard techniques. The pattern in the resolution layer (24) is transferred to the polysilane layer (22) by either using exposure to deep ultraviolet or by a fluorine-base RIE etch. This is followed by an oxygen-based RIE etch to transfer the pattern to the surface (18) of the workpiece (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.