Method for manufacturing semiconductor integrated circuits including CMOS and high-voltage electronic devices
US4892836A · kind A · utility
9Cited by
7References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 23, 1987 |
| Grant date | Jan 9, 1990 |
| Priority date | — |
| Expiry date | Mar 23, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.