High density dram trench capacitor isolation employing double epitaxial layers

US4905065A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Asim A. Selcuk · Cupertino, US
• Pau-Ling Chen · Saratoga, US
• Darrell M. Erb · Los Altos, US

Key dates

• Filing date: May 12, 1987
• Grant date: Feb 27, 1990
• Expiry date: May 12, 2007

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/37

Abstract

A new double-epitaxial structure for isolating deep (>5 .mu.m) trench capacitors (10, 10') with 1 .mu.m or less spacing (S) is disclosed. The structure comprises a thin, lightly doped upper epitaxial layer (16) on top of a thicker and more heavily doped bottom epitaxial layer (14). The low resistivity bottom epitaxial layer is intended to isolate trench capacitors of any depth. The high resistivity upper epitaxial layer is used for the CMOS periphery (22, 24) and can be selectively doped to achieve a near uniform concentration to isolate trench capacitors in the core region (20) surrounding the capacitors. Isolation between deep trenches at 1 .mu.m spacing has been demonstrated to be applicable for 4 Megabit and greater DRAM integration levels.