Semiconductor device with multilayer silicon oxide silicon nitride dielectric
US4907046A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1988 |
| Grant date | Mar 6, 1990 |
| Priority date | — |
| Expiry date | Mar 15, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/68
- WIPO fieldEngines, pumps, turbines
- WIPO sectorMechanical engineering
Abstract
A solid state device includes a transistor (A) and a capacitor (B). The capacitor is defined by a lower polycrystalline silicon layer or electrode (20), multiple dielectric layers (22), and an upper polycrystalline silicon layer or electrode (30). The dielectric layers are formed by vapor depositing a 3.6-18.6 nm thick layer of silicon nitride on the lower polycrystalline layer. Thicker silicon nitride layers increase the failure rate and decrease the capacitance (FIG. 8). More specifically, the silicon nitride layer is deposited on a thin, about 1 nm, oxidized film or surface (24) of the polycrystalline silicon layer. The silicon nitride layer is oxidized forming a silicon dioxide layer (28) until the silicon nitride layer is only about 3 nm thick. This forms on oxide layer that is 1-8.4 nm thick. If the silicon nitride layer is reduced below 3 nm, the polycrystalline silicon tends to oxidize rapidly reducing capacitance and increasing failure (FIG. 8).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.