High voltage power IC process
US4908328A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1989 |
| Grant date | Mar 13, 1990 |
| Priority date | — |
| Expiry date | Jun 6, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process is disclosed for forming an oxide isolated semiconductor wafer which can include the formation of an associated high voltage transistor. The same wafer can include a plurality of low voltage transistors which can be connected in the form of circuitry that can control the high voltage transistor. Thus, a single IC chip can be fabricated for a power control function. The process includes bonding a first wafer to a second wafer using oxide (11/14), forming a groove (18) through the oxide (15), backfilling with epitaxially regrown semiconductor (19) to provide a high voltage section, and subsequently forming the high voltage transistor, e.g. NPN or DMOS devices, in said section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.