Content addressable memory array with priority encoder
US4928260A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 1988 |
| Grant date | May 22, 1990 |
| Priority date | — |
| Expiry date | May 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90339
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory system includes a plurality of memory cells arranged in rows and columns in an array of N bit words by M word cells, a plurality of word lines extending through the array for addressing different words in the memory cells, each of the words comprising a plurality of adjacent cells extending in a first direction in the array, a plurality of match lines extending through the array in parallel with the word lines in the first direction, a plurality of bit lines extending through the array in a second direction perpendicular to the first direction, each of the bit lines communicating with the cells in one of the columns extending in the second direction, and a pair of registers connected to the bit lines for performing masking operations on bits in the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.