Optimized E.sup.2 pal cell for minimum read disturb
US4935648A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1989 |
| Grant date | Jun 19, 1990 |
| Priority date | — |
| Expiry date | Jun 16, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A four device cell is disclosed for an electrically erasable programmable logic device. The four devices include a floating gate tunnel capacitor, a floating gate read transistor having its floating gate and control gate connected respectively to the floating gate and control gate of the tunnel capacitor, a read select transistor for selectively coupling the drain of the floating gate read transistor to a product term output in response to an input term, and a write select transistor for selectively coupling the drain of the floating gate tunnel capacitor to a write data line in response to the signal on a write select line. During sensing, the control gates of all the floating gate tunnel capacitors are kept at a constant voltage V.sub.cg. The drains of all of the floating gate tunnel capacitors are also kept at a constant voltage V.sub.WDL chosen to minimize read disturb on the tunnel capacitor. Preferably V.sub.WDL =V.sub.cg .multidot.V.sub.WDL is applied to the drain of the floating gate tunnel capacitor by applying V.sub.WDL to all the write data lines and applying at least V.sub.WDL +V.sub.T to all the write select lines of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.