Method of planarization of topologies in integrated circuit structures
US4954459A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 1989 |
| Grant date | Sep 4, 1990 |
| Priority date | — |
| Expiry date | Jul 3, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/959
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer having a thickness which exceeds the height of said first portions above the remainder of the integrated circuit structure; forming a patterned mask layer over said deposited oxide layer with one or more openings therein in registry with the higher height first portions of the integrated circuit structure; etching exposed portions of said conformal oxide layer through the mask openings down to a level approximately equal to the level of the unexposed portion of the conformal oxide layer; removing the mask layer; and polishing the oxide layer to remove raised portions of the conformal oxide layer remaining after the etching step to form a highly planarized structure. Optionally, the oxide layer may be further etched anisotropically until the upper surfaces of the underlying integrated circuit structure is ex…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.