Integrated circuit chip stacking
US4956694A · kind A · utility
322Cited by
5References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 4, 1988 |
| Grant date | Sep 11, 1990 |
| Priority date | — |
| Expiry date | Nov 4, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1627
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device for increasing the density of integrated circuit chips on a printed circuit board. A plurality of integrated circuits are packaged within chip carriers and stacked, on one top of the other, on a printed circuit board. Each of the input/output data terminals, power and ground terminals of the chips are connected in parallel. Each chip is individually accessed by selectively enabling the desired chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.