One transistor flash EPROM cell
US4958321A · kind A · utility
72Cited by
3References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 22, 1988 |
| Grant date | Sep 18, 1990 |
| Priority date | — |
| Expiry date | Sep 22, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically programmable floating gate transistor useful as a one transistor flash EPROM cell includes a multi-thickness dielectric provided on a substrate. The multi-thickness dielectric limits tunnelling from a floating gate provided on the multi-thickness dielectric to a drain during programming and allowing tunnelling from the floating gate to the source during erasing. The floating gate has a low doping concentration, less than 5.times.10.sup.18 cm.sup.-3, and a thickness of less than 1000 .ANG. to provide a self-limiting erase characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.