Chi Chang
94Patents
24h-index
99Co-inventors
91Inventor score
Filing activity: Sep 22, 1988 → May 5, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5077691A | Flash EEPROM array with negative gate voltage erase operation | Physics | 246 | Expired |
| US5335198A | Flash EEPROM array with high endurance | Physics | 157 | Expired |
| US6266281A | Method of erasing non-volatile memory cells | Physics | 132 | Expired |
| US6701406B1 | PCI and MII compatible home phoneline networking alliance (HPNA) interface device | Physics | 91 | Expired |
| US4958321A | One transistor flash EPROM cell | Electricity | 72 | Expired |
| US6252803A | Automatic program disturb with intelligent soft programming for flash cells | Physics | 66 | Expired |
| US5485423A | Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS | Physics | 52 | Expired |
| US6566194B1 | Salicided gate for virtual ground arrays | Electricity | 42 | Expired |
| US6001713A | Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device | Electricity | 42 | Expired |
| US5907781A | Process for fabricating an integrated circuit with a self-aligned contact | Electricity | 41 | Expired |
| US6509232B1 | Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device | Electricity | 40 | Expired |
| US5457336A | Non-volatile memory structure including protection and structure for maintaining threshold stability | Electricity | 38 | Expired |
| US5793677A | Using floating gate devices as select gate devices for NAND flash memory and its bias scheme | Physics | 38 | Expired |
| US6645801B1 | Salicided gate for virtual ground arrays | Electricity | 37 | Expired |
| US6754105B1 | Trench side wall charge trapping dielectric flash memory device | Electricity | 36 | Expired |
| US6356482B1 | Using negative gate erase voltage to simultaneously erase two bits from a non-volatile memory cell with an oxide-nitride-oxide (ONO) gate structure | Physics | 31 | Expired |
| US7915112B2 | Metal gate stress film for mobility enhancement in FinFET device | Electricity | 31 | Active |
| US6246610A | Symmetrical program and erase scheme to improve erase time degradation in NAND devices | Physics | 30 | Expired |
| US5590076A | Channel hot-carrier page write | Physics | 28 | Expired |
| US7621173B2 | Nano-identation ultrasonic detecting system and method thereof | Physics | 27 | Active |
| US5912489A | Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory | Physics | 26 | Expired |
| US5856946A | Memory cell programming with controlled current injection | Physics | 26 | Expired |
| US6885590B1 | Memory device having A P+ gate and thin bottom oxide and method of erasing same | Electricity | 26 | Expired |
| US6664191B1 | Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space | Emerging Cross-Sectional Technologies | 26 | Expired |
| US5470773A | Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch | Electricity | 24 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.