Semiconductor memory device having stacked capacitor cells
US4970564A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1988 |
| Grant date | Nov 13, 1990 |
| Priority date | — |
| Expiry date | Dec 21, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
A semiconductor memory device having STC cells wherein major portions of active regions consisting of channel-forming portions are tilted at an angle of 45.degree. with respect to the word lines and the bit lines that meet at right angles with each other, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas. In the semiconductor memory device, furthermore, the storage capacity portions are formed even on the bit lines. Therefore, the bit lines are shielded, the capacitance between the bit lines decreases, and the memory array noise decreases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.