Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (LSSD) system
US4972414A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1989 |
| Grant date | Nov 20, 1990 |
| Priority date | — |
| Expiry date | Nov 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for identifying stuck faults in an oscillator used for providing an oscillator input signal to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of shift register latches (SRLs) are providing in the integrated circuit chip having a logical one signal applied to a data input of the SRLs. The oscillator input signal is applied to a data clock input of a first one of the SRLs and an inverted oscillator input signal is applied to the data clock input of a second one of the SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.