Method for selectively initiating/terminating a test mode in an address multiplexed DRAM and address multiplexed DRAM having such a capability
US4992985A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 1989 |
| Grant date | Feb 12, 1991 |
| Priority date | — |
| Expiry date | Mar 7, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An address multiplexed dynamic RAM device is provided which is capable of initiating (setting) and terminating (resetting) the test mode in response to the signal level combinations of the row address and column address strobe signals with the write enable signal, which signal level combinations correspond to those which are otherwise left unused in the normal operating mode thereby obviating the requirement of an additional external control signal terminal. Such initiating of the test mode can be effected by setting the RAS signal of the DRAM at a logic "low" level when the CAS signal and the WE signal are at a logic "low" level. Clearing or resetting thereof is effected by the same combination sequence, except that the WE signal is at a logic "high" level. The setting or initiating of a test mode is also implemented by the additional combination of one of the row address signal bits, e.g. the most significant bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.