Optimized electrically erasable PLA cell for minimum read disturb
US5005155A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1988 |
| Grant date | Apr 2, 1991 |
| Priority date | — |
| Expiry date | Jun 15, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A four device cell for an electrically erasable programmable logic device includes a floating gate tunnel device (sometimes referred to as a tunnel capacitor), a floating gate read transistor having its floating gate and control gate connected respectively to the floating gate and control gate of the tunnel capacitor, a read select transistor for selectively coupling the drain of the floating gate read transistor to a product term output in response to an input term, and a write select transistor for selectively coupling the drain of the floating gate tunnel capacitor to a write data line in response to the signal on a write select line. During sensing, the control gates of all the floating gate tunnel capacitors are kept at a constant voltage V.sub.cg. The drains of all of the floating gate tunnel capacitors are also kept at a constant voltage V.sub.WDL chosen to minimize read disturb on the tunnel capacitor. Preferably V.sub.WDL =V.sub.cg. V.sub.WDL is applied to the drain of the floating gate tunnel capacitor by applying V.sub.WDL to all the write data lines and applying at least V.sub.WDL +V.sub.T (where V.sub. T is a select transistor threshold voltage) to all the write select…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.