High performance overmolded electronic package
US5012386A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1989 |
| Grant date | Apr 30, 1991 |
| Priority date | — |
| Expiry date | Oct 27, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package for containing high performance electronic components, such as high speed integrated circuits (ICs). The package bears a substrate of multiple layers having a cavity therein. Leads may be placed within holes in the substrate and soldered or otherwise electrically connected to conductive patterns or layers in the substrate. A thermally conductive insert is attached to one side of the substate. The insert has a pedestal which protrudes through the cavity in the substrate. An electronic component, such as an IC may then be mounted on the pedestal and electrically connected to a conductive metal pattern on one of the layers of the substrate. This assembly may then be coated with a dielectric material to form the package body, leaving the distal ends of the leads and the back side of the insert exposed. Since the IC chip or other component is directly mounted on the insert, waste heat generated by the chip may be directly channeled outside the package through the insert which effectively forms one wall of the package. The exposed leads may be formed into the desired configuration, including shapes suitable for surface mount technology. The use of a multiple layer substate perm…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.