Self-aligned semiconductor devices
US5028555A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1990 |
| Grant date | Jul 2, 1991 |
| Priority date | — |
| Expiry date | Sep 24, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/141
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel process is provided for fabricating transistors (14), contacts (46s, 40g, 46d) and interconnections (46c) in a novel self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.m and lower. In a preferred embodiment, the configuration is also planarized. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and P.sup.+ polysilicon plugs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.