Semiconductor memory devices having stacked polycrystalline silicon transistors
US5034797A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 1990 |
| Grant date | Jul 23, 1991 |
| Priority date | — |
| Expiry date | Mar 22, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
A semiconductor device having a CMIS structure for forming a static random access memory is disclosed which device can increase the packing density of the memory and reduce the stand-by power thereof. In this semiconductor device, a first MISFET of a first conductivity type is formed on and a substrate, a second MISFET of a second conductivity type is formed over the first MISFET with a first insulating film therebetween to form a stacked CMIS structure. The second MISFET is made up of a first conductive film, a second insulating film and a second conductive film, with the source, drain and channel regions of the second MISFET being formed in the first conductive film. A first resistive drain region is formed between the channel and drain regions of the first conductive film so that an impurity of the second conductivity type is contained in the first resistive drain region at a lower concentration than in the drain region, or the first resistive drain region is substantially undoped. The first resistive drain region is disposed over the gate electrode of the first MISFET, and the gate insulating film and gate electrode of the second MISFET are formed of the second insulating film …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.