Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature
US5058115A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1989 |
| Grant date | Oct 15, 1991 |
| Priority date | — |
| Expiry date | Mar 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.