Routing system and method for integrated circuits
US5072402A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 1989 |
| Grant date | Dec 10, 1991 |
| Priority date | — |
| Expiry date | Oct 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for routing interconnections through the layout of an integrated circuit is used in conjunction with a sliceable circuit layout specification that specifies the regions of the layout occupied by circuit components, a specification of the locations of terminals in the layout, and a netlist specifying for each terminal the set of other terminals that are to be connected to it. The regions of the circuit layout not occupied by circuit components are called routing regions. The circuit layout is sequentially sliced, defining a series of rectangular channels, each of which divides a region of the circuit layout containing two or more circuit components into two circuit regions each having at least one circuit component. For each channel, if there are one or more neighboring indented routing regions, a special channel is defined for each such indentation. After the entire routing region is divided into channels and special channels, interconnections are routed through those channels and special channels. In particular, before routing interconnections through each channel, interconnections are routed through the corresponding special channels, if any. A data structure …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.