Self-aligned, planarized contacts for semiconductor devices
US5081516A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 1990 |
| Grant date | Jan 14, 1992 |
| Priority date | — |
| Expiry date | Sep 27, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel process is provided for fabricating contacts (46s, 40g, 46d) in a novel, completely self-aligned, planarized configuration for transistors (14), with self-aligned interconnections (46c). The process of the invention permits high packing densities, and allows feature distances to approach 0.5 .mu.m and lower. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defines the source (18), gate (22), and drain (20) elements and their geometry relative to each other and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and P.sup.+ polysilicon plugs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.