Semiconductor field oxidation process
US5091332A · kind A · utility
43Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1990 |
| Grant date | Feb 25, 1992 |
| Priority date | — |
| Expiry date | Nov 19, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/859
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Front end processing for a CMOS substrate resulting in the formation of n-wells, p-wells, channel stops and field oxide regions. Both the n-type and p-type dopant are implanted through silicon nitride members with one type dopant being first blocked by a first layer of photoresist and the second dopant by a second layer of photoresist. The field oxide regions are grown after the first dopant is implanted. Relatively low level ion implantation is used and additional threshold adjusting implants are not needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.