Article comprising a lattice-mismatched semiconductor heterostructure

US5091767A · kind A · utility

Assignee

• AT&T Bell Laboratories · US

Inventors

• John C. Bean · New Providence, US
• Gregg Higashi · San Jose, US
• Robert Hull · Minooka, US
• Justin L. Peticolas · Wescosville, US

Key dates

• Filing date: Mar 18, 1991
• Grant date: Feb 25, 1992
• Expiry date: Mar 18, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/405

Abstract

Disclosed are strained layer heteroepitaxial structures (e.g., GeSi/Si) that can have low threading dislocation density as well as a substantially planar surface. Furthermore, a large fraction (e.g., >90%) of the total surface are of the structure can be available for device processing. These advantageous features are achieved through utilization of novel "dislocation sinks" on or in the substrate whose height parameter h is less than or about equal to the thickness of the strained heteroepitaxial layer on the substrate. Exemplarily, h.gtoreq.h.sub.c, where h.sub.c is the critical thickness associated with misfit dislocation generation in the substrate/overlayer combination.