Optimized electrically erasable cell for minimum read disturb and associated method of sensing
US5101378A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1990 |
| Grant date | Mar 31, 1992 |
| Priority date | — |
| Expiry date | Oct 26, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory apparatus having a plurality of memory cells, each memory cell including a floating gate tunnel device (130) having a drain (134) and a floating gate read transistor (140) having a source (142) and a drain (144), the tunnel device and read transistor in each respective cell having a common floating gate (138, 148) and a common control gate (136, 146). The apparatus includes writing circuitry (102, 160) for writing desired charge levels to the floating gate of a cell to be written during a writing operation, sense circuitry (140, 150) for sensing the charge levels on the floating gate of a cell to be read during a sense operation, and circuitry for applying during the sense operation a predetermined reference voltage to the source of the read transistor in the cell to be read, and a predetermined sense mode drain voltage different from the reference voltage to the drain of the tunnel device in the cell to be read, independently of the voltage at the drain of the read transistor in the cell to be read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.