Mask alignment and measurement of critical dimensions in integrated circuits
US5109430A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1990 |
| Grant date | Apr 28, 1992 |
| Priority date | — |
| Expiry date | Oct 24, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for determining alignment and critical dimensions of regions formed on a semiconductor structure during one or more process steps includes the steps of defining a pattern A at a first location on the semiconductor device during a process step, defining a second independent pattern B at the first location on the semiconductor structure during another process step, acquiring an image of the combination A and B of both the first and second patterns, filtering that image to attenuate higher spatial frequencies while preserving lower spatial frequencies, and comparing the sign result of the filtered image with the sign result of a stored image of the individual patterns to determine alignment errors. In the preferred embodiment the step of filtering includes taking the Laplacian of Gaussian convolution of the image and saving the sign of the result. The comparison between the filtered image and the stored image uses the correlation function for the filtered images. Special circuitry is disclosed for performing the method rapidly enough to enable commercial applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.