Multilayer electrical interconnect fabrication with few process steps
US5118385A · kind A · utility
58Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 1991 |
| Grant date | Jun 2, 1992 |
| Priority date | — |
| Expiry date | May 28, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Method for making a multilayer electrical interconnect with stacked pillars between layers using a minimal number of conventional process steps. The method includes sputtering a chromium/copper/titanium trilayer on a dielectric base, depositing a patterned mask on the trilayer, etching the exposed trilayer, removing the mask, depositing a layer of polyimide over the unetched copper, forming a via in the polyimide above the copper, electrolessly plating nickel into the via, and polishing the interconnect to form a planar top surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.