Noise reducing output buffer circuit with feedback path
US5121013A · kind A · utility
19Cited by
13References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1990 |
| Grant date | Jun 9, 1992 |
| Priority date | — |
| Expiry date | Feb 12, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Electrical buffer output circuitry includes a first high branch having a high signal input terminal, a low input branch having a low input signal input terminal, and a signal output for the buffer circuitry. Either the high branch or the low branch is turned on in response to a signal at one of the input terminals, and the resistance of the turned on branch is varied as a function of time to improve the speed and noise characteristics of the buffer until the output voltage stabilizes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.