Vertical MOS transistor and its production method
US5126807A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1991 |
| Grant date | Jun 30, 1992 |
| Priority date | — |
| Expiry date | Jun 12, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
Abstract
A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. THE gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.