Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs
US5132753A · kind A · utility
46Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1990 |
| Grant date | Jul 21, 1992 |
| Priority date | — |
| Expiry date | Mar 23, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
Transistor structure using a lightly doped drain (LDD) technique are disclosed. The present invention provides a reduced on-resistance in the LDD region, while retaining substantially all the high breakdown voltage advantage of the LDD technique. The advantage of the present invention is achieved by applying a non-uniform impurity design in the LDD region, increasing gradually from the gate-edge towards the contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.