Semiconductor package utilizing edge connected semiconductor dice
US5146308A · kind A · utility
65Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1990 |
| Grant date | Sep 8, 1992 |
| Priority date | — |
| Expiry date | Oct 5, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, allowing the entire top surface of the die to be passivated, a better contact configuration, and more convenient assembly for packaging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.