Silicide formation on polysilicon
US5147820A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1991 |
| Grant date | Sep 15, 1992 |
| Priority date | — |
| Expiry date | Aug 26, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28052
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a doped polysilicon/silicide ("polycide") gate electrode. The doped polysilicon layer comprises sub-layers. The sub-layers are formed by varying the silicon deposition conditions, typically including the deposition rate, while decreasing the dopant concentration. The metal silicide layer is then formed on top of the doped polysilicon layer. An improvement in uniformity and planarity of the structure is obtained as a result of stress accommodation. In addition, the sub-layers reduce the channeling effect that occurs during high energy source/drain dopant implantation. These effects allow for a reduced stack height of the gate electrode, resulting in improvements in very small (sub-micron) device structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.