Method and apparatus for system bus testability through loopback
US5161162A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 1990 |
| Grant date | Nov 3, 1992 |
| Priority date | — |
| Expiry date | Apr 12, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/815
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A workstation or server having a central processing unit (CPU) and a standard system bus interface and loopback control logic. The I/O subsystem is tested through the application of diagnositc programs running in the CPU which use programmed I/O bus cycles to read and write from the standard system bus interface. In this way, the CPU, with the loopback test mode enabled, can functionally test data paths and controls utilized to perform programmed I/O accesses to the standard system bus interface without having to access an external system bus device. Furthermore, a loopback bus cycle can cause a direct virtual memory access (DVMA) bus cycle to be created at the system bus interface. Therefore, the CPU, with the loopback test mode enabled, can also functionally test data paths and controls utilized to perform system memory DVMA without the presence of an external system bus device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.