BiCMOS semiconductor device
US5173760A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1990 |
| Grant date | Dec 22, 1992 |
| Priority date | — |
| Expiry date | Mar 26, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0109
Abstract
A method for fabricating a BiCMOS device to achieve a maximum performance through a minimum processing steps, in which the BiCMOS device comprises high integration and high performance MOS transistors, self-aligned metal contact emitter type bipolar transistors having high load driving force, high performance matching characteristics and high integration, and self-aligned polycrystalline silicon emitter type bipolar transistors having high integration and high speed characteristics in low current, thereby being used in high integration, high speed digital and precise analog system. Said method comprises a plurality of fabrication steps including ion-implantation, formation of thin film oxide layer, deposition of nitride layer, etching of oxide layer, formation of windows and others, alternately or/and sequentially in a single chip substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.