Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors

US5175120A · kind A · utility

Assignee

• Micron Technology, Inc. · US

Inventor

• Roger Lee · Boise, US

Key dates

• Filing date: Oct 11, 1991
• Grant date: Dec 29, 1992
• Expiry date: Oct 11, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

Disclosed is a process for fabricating a semiconductor wafer to form a memory array and peripheral area, where the array comprises nonvolatile memory devices employing floating gate transistors and the peripheral area comprises CMOS transistors. A first layer of conductive material is applied atop insulating layers. A dielectric layer is applied atop the first conductive layer for use in floating gate transistors within the array. The dielectric layer and first conductive material are etched from the peripheral area, leaving patterned dielectric material and first conductive material in the array. A second layer of conductive material is applied atop the wafer to cover the peripheral area and dielectric layer of the array. The conductive and dielectric materials of the array are patterned and etched separately from the patterning and etching of conductive material of each of the first and second conductivity type CMOS transistors of the peripheral area. As well, the conductive material of the first conductivity type CMOS transistors of the peripheral area are patterned and etched separately from the patterning and etching of each of, a) conductive and dielectric materials of the ar…