Semiconductor chip interposer module with engineering change wiring and distributed decoupling capacitance
US5177594A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1991 |
| Grant date | Jan 5, 1993 |
| Priority date | — |
| Expiry date | Dec 13, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15312
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is described for supporting and interconnecting semiconductor chips, each chip having contact lands on a contact surface, the package also including a substrate with a contact surface. An interposer module is disposed between at least one chip's contact surface and the substrate's contact surface. The interposer module has first and second opposed surfaces and a first plurality of contact locations positioned on its first surface which mate with a chip's contact land. A second plurality of contact locations on the interposer modules second surface are positioned to mate with contact lands on the substrate. A set of conductive vias are positioned within the interposer module and connect the first plurality of contact locations with a first subset of the second plurality of contact locations. A distributed capacitance layer is positioned within the interposer and is adjacent to its first surface. Adjacent to the second surface are X and Y lines which can be used to make engineering change interconnections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.