Data output stage having feedback loops to precharge the output node
US5179300A · kind A · utility
24Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1991 |
| Grant date | Jan 12, 1993 |
| Priority date | — |
| Expiry date | Apr 26, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data output stage of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors associated to drive an output node of said stage, comprises first and second feedback loops which are structurally independent and respectively connected between said node and a corresponding gate electrode of each transistor to precharge said output node at a predetermined value and reduce the noise to ground during the switching phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.