Control of backgate bias for low power high speed CMOS/SOI devices
US5185535A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 1991 |
| Grant date | Feb 9, 1993 |
| Priority date | — |
| Expiry date | Jun 17, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/901
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate. By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair. The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N- silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.