Memory array architecture for flash memory
US5185718A · kind A · utility
61Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1991 |
| Grant date | Feb 9, 1993 |
| Priority date | — |
| Expiry date | Feb 19, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a EEPROM flash memory array utilizing single transistor cells to provide read/write nonvolatile storage. The array includes a plurality of sectors, each oriented along the word line direction, and the sectors may include one or more word lines. An erase select transistor is provided for each sector and each word line includes a pass gate transistor which assists in both the programming and the erase operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.