Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization
US5192708A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 1991 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Apr 29, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of providing sublayer contacts in vertical walled trenches is proposed. In accordance with the present invention, the phosphorus doped amorphous silicon is deposited at temperatures less than 570.degree. C. The conversion into the extremely large crystal low resistivity polysilicon is accomplished by a low temperature anneal at 400.degree. C. to 500.degree. C. for several hours and a short rapid thermal anneal (RTA) treatment at a high temperature approximately 850.degree. C. for twenty seconds. These two conversion heat treatments are done at sufficiently low thermal budget to prevent any significant dopant movement within a shallow junction transistor. After anneal, the excess low resistivity silicon is planarized away by known techniques such as chemical/mechanical polishing. In addition, due to the trench filling abilities of the amorphous silicon CVD process, in one preferred embodiment of the invention the capability of accessing subsurface silcon layers at different trench depths is demonstrated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.