Integrated parity-based testing for integrated circuits
US5193092A · kind A · utility
10Cited by
1References
8Claims
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Key dates
| Filing date | Dec 20, 1990 |
| Grant date | Mar 9, 1993 |
| Priority date | — |
| Expiry date | Dec 20, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/83
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit includes parity chains which serve as test logic. Each parity chain has a series of XOR gates, where one input to each succeeding XOR gate in a chain is tied to the output of the preceding XOR gate. The remaining inputs are tied to nodes of the main logic, thus defining test points. An error at any one of the test points is reflected in the output of the parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register which provides a serial signature which can be analyzed to detect integrated circuit defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.