Mark R. Hartoog
11Patents
10h-index
18Co-inventors
61Inventor score
Filing activity: Dec 13, 1990 → May 30, 1997
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5856927A | Method for automatically routing circuits of very large scale integration (VLSI) | Electricity | 85 | Expired |
| US5638291A | Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew | Physics | 49 | Expired |
| US5974245A | Method and apparatus for making integrated circuits by inserting buffers into a netlist | Physics | 49 | Expired |
| US5313079A | Gate array bases with flexible routing | Emerging Cross-Sectional Technologies | 37 | Expired |
| US5197015A | System and method for setting capacitive constraints on synthesized logic circuits | Physics | 31 | Expired |
| US5521836A | Method for determining instance placements in circuit layouts | Physics | 29 | Expired |
| US5367469A | Predictive capacitance layout method for integrated circuits | Physics | 22 | Expired |
| US5399517A | Method of routing three layer metal gate arrays using a channel router | Emerging Cross-Sectional Technologies | 14 | Expired |
| US5295088A | Method for predicting capacitance of connection nets on an integrated circuit | Electricity | 10 | Expired |
| US5193092A | Integrated parity-based testing for integrated circuits | Physics | 10 | Expired |
| USRE35671E | Predictive capacitance layout method for integrated circuits | General | 7 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.