Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor

US5196357A · kind A · utility

Assignee

• VLSI Technology, Inc. · US

Inventors

• William J. Boardman · Danville, US
• Ying-Tsong Loh · Saratoga, US
• Edward D. Nowak · Pleasanton, US
• Chung S. Wang · Fremont, US

Key dates

• Filing date: Nov 18, 1991
• Grant date: Mar 23, 1993
• Expiry date: Nov 18, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0273

Abstract

For a structure with an overlapping gate region, a first insulator layer is placed on a substrate. A source/drain polysilicon layer is placed on the insulator layer. The source/drain polysilicon layer is doped with atoms of a first conductivity type. A second insulator layer is placed on the source/drain polysilicon layer. A gap is etched in the second insulator layer and the source/drain polysilicon layer to expose a portion of the first insulator layer. The exposed portion of the first insulator layer and an additional amount of the first insulator layer under the second insulator is etched so as to enlarge the gap and to undercut a portion of the source/drain polysilicon layer. Two polysilicon filler regions are formed which fill a portion of the gap including the undercut area under the source/drain polysilicon layer. A gate polysilicon region is formed in the gap and extends over the source/drain polysilicon layer. The gate polysilicon region is separated from the source/drain polysilicon layer and the polysilicon filler regions by a dielectric region. Source/drain regions are formed by atoms in the source/drain polysilicon layer diffusing through the polysilicon filler region…