Chung S. Wang
10Patents
8h-index
10Co-inventors
65Inventor score
Filing activity: Nov 30, 1983 → Jun 6, 1995
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5496751A | Method of forming an ESD and hot carrier resistant integrated circuit structure | Electricity | 36 | Expired |
| US5631485A | ESD and hot carrier resistant integrated circuit structure | Electricity | 29 | Expired |
| US5196357A | Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor | Electricity | 28 | Expired |
| US5411906A | Method of fabricating auxiliary gate lightly doped drain (AGLDD) structure with dielectric sidewalls | Electricity | 22 | Expired |
| US5444003A | Method and structure for creating a self-aligned bicmos-compatible bipolar transistor with a laterally graded emitter structure | Electricity | 18 | Expired |
| US5227320A | Method for producing gate overlapped lightly doped drain (GOLDD) structure for submicron transistor | Electricity | 17 | Expired |
| US5340761A | Self-aligned contacts with gate overlapped lightly doped drain (goldd) structure | Electricity | 16 | Expired |
| US5288652A | BICMOS-compatible method for creating a bipolar transistor with laterally graded emitter structure | Emerging Cross-Sectional Technologies | 14 | Expired |
| US4521446A | Method for depositing polysilicon over TiO.sub.2 | Electricity | 7 | Expired |
| US4574177A | Plasma etch method for TiO.sub.2 | Emerging Cross-Sectional Technologies | 4 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.