System and method for setting capacitive constraints on synthesized logic circuits
US5197015A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1990 |
| Grant date | Mar 23, 1993 |
| Priority date | — |
| Expiry date | Dec 20, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer aided design system, capacitative constraints are defined for the nodes of an integrated circuit. A netlist specifies the integrated circuit's components and a set of interconnecting nodes. Also provided are a set of timing constraints for propagation of signals from specified input nodes to specified output nodes, and a set of signal delays associated with the circuit's components. The process begins by assigning a time delay value and a corresponding initial maximum capacitance value to each circuit node, consistent with the specified timing constraints. Next, a routing difficulty value for the entire circuit, equal to a sum of routing difficulty values associated with the circuits's nodes is computed. Each routing difficulty value is a predefined function of the maximum capacitance value for a corresponding node and the number of circuit components coupled to that node. Then, the following steps are repeated until changes in the computed routing difficulty value for the entire circuit meet predefined criteria. Beginning with components coupled to output nodes and progressing toward components adjacent input nodes, the time delay associated with a component's output…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.