Output pad electrostatic discharge protection circuit for MOS devices
US5208719A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 1991 |
| Grant date | May 4, 1993 |
| Priority date | — |
| Expiry date | Aug 20, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit protects the series coupled PMOS-NMOS transistor output stage, input stage or input/output stage commonly found in a CMOS device from output pad ESD, whether or not the CMOS device is mounted in a circuit board or coupled to a power source. The circuit includes a second PMOS transistor whose output leads are coupled between the output pad and the gate of the output NMOS transistor, and also includes a resistor coupled between the gate of this second PMOS transistor and a voltage source node. A positive potential ESD at the output pad will turn on the second PMOS transistor, thereby coupling positive ESD potential to the gate of the output NMOS transistor. This causes the output NMOS transistor to turn on, avoiding the "snapback" mode destruction that would occur if the second PMOS transistor were not present. The resistor cooperates with the intrinsic capacitance present at the gate of the second PMOS transistor to form an RC filter that prevents noise transients coupled to this gate from turning on the second PMOS transistor. A second preferred embodiment is a protective circuit that includes the above described series coupled output PMOS, NMOS transistors, the second PM…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.