Circuit for providing synchronous refresh cycles in self-refreshing interruptable DRAMs
US5208779A · kind A · utility
28Cited by
9References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1991 |
| Grant date | May 4, 1993 |
| Priority date | — |
| Expiry date | Apr 15, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is a circuit for synchronizing the refresh cycles of a bank of self-refreshing interruptable DRAMs. The refresh cycles are synchronized through a bidirectional control path from each self-refreshing interruptable DRAM to its respective external refresh pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.