Process for fabricating a flash EPROM having reduced cell size

US5210047A · kind A · utility

Inventors

• Been-Jon Woo · Saratoga, US
• Gregory E. Atwood · San Jose, US
• Stefan Lai · Atherton, US
• T. C. Ong · San Jose, US

Key dates

• Filing date: Dec 12, 1991
• Grant date: May 11, 1993
• Expiry date: Dec 12, 2011

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S148/05

Abstract

A process for fabricating an electrically programmable read-only memory array having increased density includes forming recessed field oxide regions in a silicon substrate. Elongated parallel wordline stacks are then formed over the surface of the substrate. Source and drain regions are formed by ion implantation in the openings between these vertical stacks. These openings are then filled with a metal layer until the wafer is substantially planar. This metal layer is then patterned to form drain contact pads and V.sub.SS interconnect strips. The V.sub.SS interconnect strips contact adjacent source regions across field oxide regions that insulate adjacent memory cells.