Method for fabricating a semiconductor memory cell
US5219780A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1992 |
| Grant date | Jun 15, 1993 |
| Priority date | — |
| Expiry date | Mar 12, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/318
Abstract
The present invention relates to a method for fabricating a semiconductor memory cell consisting of a switching transistor and a capacitor wherein a polysilicon pad and a polysilicon storage node are simultaneously patterned with a self-alignment method without a mask. Accordingly, the present invention has the following advantages: First, the overlay accuracy can be improved by patterning a polysilicon pad and a polysilicon storage node with a self-alignment method. Second, the fabrication process can be simpler than the prior fabrication process for the semiconductor memory cell of a noble stacked capacitor cell structure. Third, the storage capacitance of a capacitor can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.