Package for an integrated circuit structure
US5223741A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1989 |
| Grant date | Jun 29, 1993 |
| Priority date | — |
| Expiry date | Sep 1, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package for housing a large scale semiconductor integrated circuit structure, such as a wafer or an assemblage of chips in a hybrid configuration, comprises a heat spreading and dissipating base plate to which the wafer or hybrid circuit is directly bonded. Electrical connections from the periphery of the package interior to the wafer are preferably made with equal length TAB (Tape Automated Bonding) strips connected to electrically conductive pads located along a diameter of the wafer or the centerline of the hybrid circuit. If hermeticity is desired, the integrated circuit structure is encircled by a boundary strip of sandwich construction through which signals are routed, and to which a lid is attached. For hermeticity, the integrated circuit structure is surrounded on all sides with a barrier combining metal and ceramic; the remainder of the package may be constructed from conventional printed circuit board materials. The package can be made arbitrarily large without encountering the problems typically associated with hermetic structures which utilize large areas of ceramic materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.